The field of the present invention pertains to semiconductor fabrication processes. More particularly, the present invention relates to the field of chemical mechanical polishing of a semiconductor wafer.
Most of the power and usefulness of today""s digital integrated circuit (IC) devices can be attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or IC. The starting material for typical ICs is very high purity silicon. The material is grown as a single crystal. It takes the shape of a solid cylinder. This crystal is then sawed (like a slice of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components is commonly defined photographically through a process known as photolithography. The photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. Very fine surface geometry can be accurately produced by this technique. To improve performance of ICs, the density of circuits on a semiconductor wafer is increased. To increase the density of the circuits on the semiconductor wafer, the size of the circuits must be decreased. As the size of the circuits decrease, they become more sensitive to tolerances in the manufacturing operations that create the finished semiconductor wafer. In response to the continued demand for circuit miniaturization, a need arises for improving tolerances in the manufacturing operations that create the finished semiconductor wafer.
One of the sources of manufacturing variation for producing the semiconductor wafer is Chemical mechanical polishing (CMP). CMP is a preferred method of obtaining full planarization of a semiconductor wafer. It involves removing a sacrificial layer of dielectric material using mechanical contact between the wafer and a moving polishing pad saturated with slurry. Polishing flattens out height differences, since high areas of topography (hills) are removed faster than areas of low topography (valleys). Polishing is the only technique with the capability of smoothing out topography over millimeter scale planarization distances leading to maximum angles of much less than one degree after polishing. However, the CMP operation possess variables that affect the flatness, smoothness, and overall consistency of the semiconductor wafer after polishing. Hence, to improve the consistency of the semiconductor wafer following polishing, a need arises to better control the variation in the CMP operation.
One example of the problems that might arise from the CMP operation is the polishing to form metal lines in a semiconductor wafer using the CMP process. For instance, to couple the various discrete components of a circuit, a conductor pattern of lines is constructed between the components formed on the wafer. The conductor pattern is formed in a manner similar to that used to form the semiconductor devices. Oxidation is used to create a dielectric layer to isolate the conductor from the semiconductor portion of the wafer. Etching is used to define trenches for conductors. Chemical or physical vapor deposition is used to deposit a metal (e.g., copper) layer on the dielectric layer. Finally, chemical mechanical polishing (CMP) is typically used to remove the layer of metal from specific areas, usually the non-trench areas of the wafer that are not designed to be conductors. After the polishing operation, metal still remains within the trenches. The resultant product is a semiconductor wafer with metal-filled trenches that couple components.
However, due to the small size of components on conventional ICs, metal lines and other components of the semiconductor wafer are very sensitive to variation in the CMP process. The variations may affect the features or characteristics of the formed metal lines and the components. One potential source of variation is contaminants arising in the polishing operation. Contaminants may include oxygen, water moisture, and any other item that detrimentally affects the polishing operation . The oxygen causes oxidation to occur in elements and compounds. Contaminants can affect the polishing rate, the final geometry, physical properties, and subsequent operations of components in the semiconductor wafer. Hence, a need arises to eliminate contaminants in the CMP process.
Prior Art FIG. 1A is a top view of a chemical mechanical polishing (CMP) machine 100 and Prior Art FIG. 1B is a side view of CMP machine 100. CMP machine 100 is fed semiconductor wafers to be polished. CMP machine 100 picks up the wafers with an arm 101 and places them onto a rotating polishing pad 102. Polishing pad 102 is made of a resilient material and is textured, often with a plurality of predetermined grooves 103, to aid the polishing process. Polishing pad 102 rotates on a platen 104, or turntable located beneath polishing pad 102, at a predetermined speed. A wafer 105 is held in place on polishing pad 102 within a carrier ring 112 that is connected to a carrier film 106 of arm 101. The front surface of wafer 105 rests against polishing pad 102. The back surface of wafer 105 is against the lower surface of carrier film 106 of arm 101. As polishing pad 102 rotates, arm 101 rotates wafer 105 at a predetermined rate. Arm 101 forces wafer 105 into polishing pad 102 with a predetermined amount of down force. CMP machine 100 also includes a slurry dispense arm 107 extending across the radius of polishing pad 102, which dispenses a flow of slurry onto polishing pad 102.
To aid in maintaining a stable removal rate, CMP machine 100 includes a conditioner assembly 120. Conditioner assembly 120 includes a conditioner arm 108, which extends across the radius of polishing pad 102. An end effector 109 is connected to conditioner arm 108. End effector 109 includes an abrasive conditioning disk 110 that is used to roughen the surface of polishing pad 102. Conditioning disk 110 is rotated by conditioner arm 108 and is transitionally moved towards the center of the polishing pad 102 and away from the center of polishing pad 102, such that conditioning disk 110 covers the radius of polishing pad 102. In so doing, conditioning disk 110 covers the surface area of polishing pad 102, as polishing pad 102 rotates. A polishing pad having a roughened surface has an increased number of micro-pits and gouges in its surface from conditioner assembly 120 and therefore produces a faster removal rate via increased slurry transfer to the surface of wafer 105. Without conditioning, the surface of polishing pad 102 is smoothed during the polishing process and removal rate decreases dramatically. Conditioner assembly 120 re-roughens the surface of polishing pad 102, thereby improving the transport of slurry and improving the removal rate.
As described above, the CMP process uses abrasive slurry on a polishing pad. The polishing action of the slurry is comprised of an abrasive frictional component and a chemical component. The abrasive frictional component is due to the friction between the surface of the polishing pad, the surface of the wafer, and the abrasive particles suspended in the slurry. The chemical component is due to the presence in the slurry of polishing agents that chemically interact with the material of the dielectric layer of wafer 105. The chemical component of the slurry is used to soften the surface of the dielectric layer to be polished, while the frictional component removes material from the surface of wafer 105.
Prior art FIG. 2A illustrates a top view, and Prior Art FIG. 2B a cross-section view 1xe2x80x941, of a semiconductor wafer 200 following the conventional CMP process. The resultant metal line 202 formed in oxide layer 204 of semiconductor wafer 200 by a conventional CMP process can have many defects. Some of the potential defects are illustrated herein.
One possible effect of contaminants in the CMP operation is the formation of oxidation layer on a component in semiconductor wafer. As an example, an oxidation layer 208 formed on metal line 202, or some other portion of semiconductor wafer 200, from the presence of oxygen, water moisture, or other contaminants near the semiconductor wafer 200 before, during, or after the CMP operation. Oxidation layer 208 may affect subsequent fabrication operations on semiconductor wafer 200 such as adhesion of subsequently deposited layers of material. Likewise, oxidation layer 208 may affect the functional characteristics, such as resistance or heat dissipation, of components such as metal line 202. Oxide layer 208 may be a build-up on a portion of semiconductor wafer 200, or it may consume a portion of semiconductor wafer 200 during the oxidation process.
Likewise, the presence of physical contaminants such as dirt or physical particles may affect the flatness or smoothness of the finished semiconductor wafer 200. The particles may be of a size, hardness, or characteristic that detrimentally affects the CMP operation. For example, if a contaminant having an adhesive property contaminated a portion or all of semiconductor wafer 200 prior to, during, or after the CMP operation, the abrasive slurry may not polish the contaminated area in a same pattern or flatness as the uncontaminated portion of semiconductor wafer. As a final example, the contaminant may be larger and harder than the abrasive slurry, and consequently, cause an excessive wear, or a gouge 206 on a portion of semiconductor wafer 200. A gouge can cause an electrical short, adverse physical characteristics, etc. within semiconductor wafer 200. Hence, a need arises to eliminate oxygen, foreign particles, and moisture contaminants in the CMP operation.
In summary, a need exists for a method and system for improving tolerances in the manufacturing operations that create the finished semiconductor wafer. More specifically, a need exists to improve the consistency of the semiconductor wafer polishing process by reducing the variation in the CMP operation. Finally, a need arises to eliminate contaminants in the CMP process. More specifically, a need arises to eliminate oxygen, foreign particles, and moisture contaminants in the CMP operation. The present invention provides a unique and novel solution that meets all the above needs.
The present invention provides a method and system for improving tolerances in the manufacturing operations that create the finished semiconductor wafer. More specifically, the present invention improves the consistency of the semiconductor wafer polishing process by reducing the variation in the CMP operation. Finally, the present invention eliminates contaminants in the CMP process. More specifically, the present invention eliminates oxygen, foreign particles, and moisture contaminants in the CMP operation.
One embodiment of the present invention is a system for performing a chemical mechanical polishing (CMP) operation on a semiconductor wafer. The system is comprised of a chemical mechanical polishing (CMP) machine, a gas manifold and a gas hood. The CMP machine is for polishing a surface of a semiconductor wafer. The CMP machine is comprised of a polishing platen, a carrier and a drive mechanism coupling the polishing platen and the carrier. The gas manifold is coupled to the CMP machine and it supplies gas to the CMP machine. Finally, the gas hood is coupled to the gas manifold. The gas hood is operational for providing a blanket of gas around the semiconductor wafer for the CMP polishing operation.
Another embodiment of the present invention provides a sealed chamber enclosing the CMP machine. The sealed chamber provides an environment where atmospheric gasses can be evacuated from around the semiconductor wafer, and an inert gas injected to surround the semiconductor water. The sealed chamber helps to contain the inert gas, and thereby reduces the consumption, and increases the efficiency, of inert gas during the CMP operation.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.